PULP is a RISC-V architecture which has peripherals interconnected with micro DMA system. This Verification Environment is designed to validate the peripherals with microDMA system with in the PULP platform. Presently, It has ability to verifying SPI and UART protocols, with plans to extends its capabilities to other peripherals in the future. Leveraging the UVM library, it facilitates the creation of reusable verification components and test environments using SystemVerilog.
Application
We are concentrating on enhancing PULP uDMA system with peripherals. This Verification Environment is contained several UVM agents. Like UDMA_TX, UDMA_RX, SPI, UART, Config agent, command agents. Let’s consider one peripheral like SPI. When we need to verify SPI, I have developed reusable UDMA TX and UDMA RX agents. Then we have developed SPI agent, CMD agent (command agent). This SPI agent and UART agent has the capability of both RX and TX communication modes ( only SPI it has full_duplex mode also). When we consider TX mode of the SPI. Firstly we have to start sequence of the CMD agent with respect to TX communication mode. Then we have to run both UDMA_TX and SPI agent for TX communication. This moment SPI agent act as a passive agent. While we run both agents, I have to make checkers and predictors for comparison. Then the result of the Verification will show on the dashboard. Same as TX we can Verity to RX and full duplex. Also we have several tests with different configurations. This environment has capability to run a specific test or we can run regression test. For regression I have developed an python script.
There will be huge probability for integrating PULP RISC-V architecture to industrial applications. So Using Our Verification Environment Then can easily verify their own peripherals and also common peripherals. For common peripheral like UART, SPI, I2C etc, We have developed the UVM agents. Anyone easily connect and easily validate their protocol.