AXI4S FIFO test unit

This will help to verify modules which contains AXI4-Stream ports. This is a project which I have done with Accelr team. The purpose of this VIP is to facilitate the verification process of RTL DUTs that utilize the AXI4-Stream protocol. By integrating our VIP, design and verification engineers gain the ability to customize packets that adhere to the AXI4-Stream protocol, enabling comprehensive testing of their designs.

We used existing VIP which is Xilinx AXI4-Stream VIP but it verifies at beat level which is not a powerfull abstract. Our VIP allows to verify AXI-Stream packet level verifications. What users only need to do implement the model (model of the DUT).

Github repo shows an example with AXIS FiFo

Github link : https://github.com/accelr-net/axis_fifo_unit_test