PULP is a RISC-V architecture which has peripherals interconnected with micro DMA system. This Verification Environment is designed to validate the peripherals with microDMA system with in the PULP platform. Presently, It has ability to verifying SPI and UART protocols, with plans to extends its capabilities to other peripherals in the future. Leveraging the UVM library, it facilitates the creation of reusable verification components and test environments using SystemVerilog.
Application We are concentrating on enhancing PULP uDMA system with peripherals....
AXI4S FIFO test unit This will help to verify modules which contains AXI4-Stream ports. This is a project which I have done with Accelr team. The purpose of this VIP is to facilitate the verification process of RTL DUTs that utilize the AXI4-Stream protocol. By integrating our VIP, design and verification engineers gain the ability to customize packets that adhere to the AXI4-Stream protocol, enabling comprehensive testing of their designs....
Abstract Cleaning is the most common household task we perform in our everyday life. For kids ages 2 to 5, tidying up their room and vacuum cleaning the house is a challenging and tiring task that most people faced in their day-to-day life. This report presents our Final Year Project of Intelligent Floor Cleaning Robot that can perform Object arrangement and Tidy up tasks in the Kids’ Room and efficient cleaning tasks for the Living Room....